Development of a radio mode for the long wavelength array (LWA) receiving system to study the equatorial aeronomy

Instituto Geofísico del Perú (IGP), through its scientific facility at the Jicamarca Radio Observatory (JRO), monitors the upper atmosphere with different instruments: radars, GNSS receivers, magnetometers, and others. Through a NSF MRI award, two long wavelength array (LWA) reception stations will be installed in 5 50 km south (Santa María) and 170 km east (Huancayo) of Jicamarca. Each station is composed of 256 dual-polarization antennas circularly distributed with a diameter of 100 m. The systems will be constructed based on the system developed and installed at the University of New Mexico.

Implementing a tristatic radar system at Jicamarca would enhance different types of observations, requiring the establishment of two receiving stations near IGP-JRO. The receiving stations of Santa María and Huancayo would enable independent, passive radio astronomy observations. Furthermore, the combined stations would provide 3D Doppler information. To expand the capabilities to monitor the equatorial ionosphere, we present the development of the radio receiver mode for the long wavelength array (LWA). The radio receiver consists of 16 AMD Zynq UltraScale+ MPSoC ZCU102 and 128 ADS5296A ADCs, configured for 12-bit resolution with a sampling rate of 160 MSPS. The system supports the demodulation of radio frequency signals from 1 MHz to 80 MHz from other radars. This work focuses on the characterization and processing of signals at 49.92 MHz and 32.5 MHz, transmitted by the Jicamarca and SIMONe radars, respectively.

The hardware synthesis was based on the VHDL hardware description language, using a behavioral description style for the modules, such as the SPI controller, register map, numerically controlled oscillator (NCO), demodulator, DSP, beamforming, and data transfer. Additionally, the Arm Cortex-A53 integrated into the ZCU102 was also used for register writing through the SPI protocol. We tested the developed radio receiver using a testbench in the Xilinx-AMD Vivado development environment. The next step involves integrating all the mentioned modules and the IP Core Clocking Wizard using the structural description style in Vivado. Subsequently, the ADCs will undergo evaluation using the copper ball experiment, followed by the initial data acquisition tests at the IGP-JRO facilities.