JRO digital receiver modernization: PCB design with an SDR approach

The latest data acquisition system running at the Jicamarca Radio Observatory for the main radar has been used for more than six years now. Although there are no major inconveniences on the performance there have been some problems with internal interference which are usually unpredictable and related to the PCB design. Because of this we believe there are some chances of improvement on developing a new design. We propose a new design for the digital receivers with an SDR-like approach, this will let us manage all the data directly from the ADC which wasn't possible on the previous design and at the same time will extend the frequency range and bandwidth for other radars or radio applications. All the digital processing will be made inside an FPGA. This poster will explain in summary the different parts of the PCB design and the choices we made to improve the performance, it has been more carefully designed taking into account all possible sources of interference and signal integrity too.