On the FPGA-Based LWA Receiver for the J-ARGUS project: Digital Signal Processing and Hardware Verification
The Jicamarca-Augmented Radar for Geospace and Upper Atmosphere Studies (J-ARGUS) is an effort to upgrade the Jicamarca Radio Observatory (JRO) radar from a monostatic to a tristatic configuration. This will be achieved by developing two new receiving stations, one located to the east of Jicamarca, in Huancayo, and another located to the south, in Santa Maria. The stations will be based on the Long Wavelength Array (LWA) radio telescope architecture.
J-ARGUS will advance the observational capabilities of JRO and will benefit various areas of research, including, but not limited to, meteor science, ionospheric irregularities, ionospheric electrodynamics, and meteor afterglows. Additionally, the system will expand Jicamarca's services to the field of radio astronomy.
As part of this effort, J-ARGUS will utilize a new version of the LWA digital receiver whose design has been led by the University of New Mexico (UNM). The new receiver will feature a processing chain powered by the Zynq UltraScale+ MPSoC (on the ZCU102 development board). This platform integrates ARM processing cores with a Field Programmable Gate Array (FPGA), allowing for on-demand reprogramming of synthesizable digital signal processing (DSP) hardware modules to support diverse observational modes.
In this poster, we will describe the J-ARGUS project and detail the contributions the University of Texas at Dallas (UTD) has made to support the project’s development and enable the participation of undergraduate students. More specifically, these contributions include hardware verification of the ZCU102 and its companion digitizer boards. By utilizing manufacturer-supplied and custom test benches, we identify hardware faults preemptively to reduce field deployment costs and failures. This testing has already identified potential faults in hardware components and prevented them from being deployed erroneously. Furthermore, we are performing development at UTD of key synthesizable hardware modules for a subset of the J-ARGUS system components, including a Low Voltage Differential Signaling (LVDS) interface for digitizer output deserialization, a local oscillator, low-pass filter, and decimator for signal conditioning, and a high-speed data transfer module for FPGA-to-processor offloading.